The present invention relates to a process for manufacturing semiconductor devices, and particularly to a process for manufacturing semiconductor devices capable of forming an SOI structure in which the laminate structure between a semiconductor and an insulator has good interface properties to such an extent that it can be used as a channel region and a gate insulating film in MOSFET's for LSI's.
Electronic computers and communication equipment have been developed rapidly. In recent years, in particular, a plurality of computers are coupled through communication circuits to form a network in an attempt to realize high degree of functions, opening the door toward the age of information. Therefore, it is urged to develop these equipment to meet the needs of the times, and it is desired to provide large-scale integrated circuits (LSI's) which are fundamental parts and which operate at higher speeds maintaining higher degree of integration. The conventional method to meet this demand was chiefly to scale down the elements. In the future, however, it is considered that the three dimensional integrated circuits and new device concept and/or designs employing the SOI (silicon on insulator) structure will play a leading role. Examples of such devices are shown in FIGS. 8A and 8B.
FIG. 8A is a section view of a three dimensional integrated circuit, and FIG. 8B is a section view showing a one-gate-wide CMOS inverter which is a transistor of a new structure reported in a paper entitled "One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon" disclosed in IEEE Electron Devices Letters, Vol. EDL-1, No. 6, June, 1980, pp. 117-118 by J.F. Gibbons and K.F. Lee. In either device, a MOS-type field effect transistor (MOSFET) formed in a silicon layer 6 on an insulating film 5 works as a fundamental element. In FIG. 8A, a portion surrounded by a dot-dash line represents a MOSFET. Here, the one-gate-wide CMOS inverter stands for a complementary MOSFET (CMOS) in which the two upper and lower MOSFET's share a single gate electrode 1 as schematically shown in FIG. 9.
The conventional technique for forming the SOI structure can be roughly divided into a method of forming single crystalline silicon on an insulating film or on an insulating substrate, and a method of forming an insulating layer in a single crystalline silicon substrate. An example of the former method includes a technique according to which polycrystalline silicon deposited on an insulating film such as SiO.sub.2 is crystallized by laser annealing, electron beam annealing or strip heater annealing. An example of the latter method includes a technique according to which a damaged layer is formed in the substrate by hydrogen ion implantation, and the damaged layer that can be easily oxidized is selectively oxidized, or a technique which forms an SiO.sub.2 layer in the silicon substrate by oxygen ion implantation. Owing to such technique, at present, it is made possible to form an SOI of good crystallinity which is capable of forming a MOSFET. However, none of the SOI structures formed by these methods exhibit good electric properties on the interface between the silicon layer 6 and the insulating layer 5. If the MOSFET is formed as shown in FIG. 8A, the interface 32 between the insulating film 5 and the silicon layer 6 formed thereon serves as a path for a leakage current across the source 2 and the drain 3, and the element exhibits quite poor performance.
To avoid this problem, therefore, a method was contrived to form a channel stopper by implanting impurity ions into the interface 32, presenting considerably improved results.
However, when an underlying insulating film 5 is to be used as a gate insulating film 4 which is as thin as 5 to 100 nm as in a MOSFET formed in the upper layer of the one-gate-wide CMOS inverter shown in FIG. 8B, a channel is formed in the interface 33 between the underlying insulating film 5 and the silicon layer 6 formed thereon. Therefore, the above-mentioned problem becomes so serious that none of the above-mentioned methods is effective; i.e., the problem remains unsolved.
In FIGS. 8A, 8B and 9, reference numeral 1 denotes a gate electrode, 2 denotes a source region, 3 denotes a drain region, 4 denotes a gate insulating film, 5 denotes an underlying insulating film, 6 denotes a silicon layer, 7 denotes a silicon substrate, and 32 and 33 denote interfaces between the underlying insulating film and the silicon layer.